The present invention relates to a clock generating circuit for generating a clock signal capable of reducing EMI noise and a semiconductor integrated circuit using the clock generating circuit.
Recently, the operational speed in semiconductor integrated circuits is greatly increasing with progress of the semiconductor manufacturing process. Thus, the operational speed, for example, of the output buffer within the semiconductor integrated circuit is also highly increasing. For example, a recent SDRAM may operate at a speed equal to or higher than 100 MHz and thus the data bus will also be operated with a frequency equal to or higher than 100 MHz.
Such a high-speed data bus tends to produce increased noise due to the electromagnetic wave emitted from the printed circuit board. Various standards limiting such emitted electromagnetic wave noise have been established. Accordingly, the emitted electromagnetic wave noise shall not exceed the upper limit of noise level which is established for each frequency band.
The electromagnetic wave noise emitted from electronic instruments is generally known as xe2x80x9cEMI noisexe2x80x9d or simply xe2x80x9cEMIxe2x80x9d.
FIG. 18 exemplifies an EMI noise spectrum obtained by measuring EMI noises from an electronic instrument for each frequency. In this figure, the horizontal axis represents the frequency while the vertical axis depicts the noise level (or electromagnetic wave intensity).
Since the general digital electronic instruments operate with a clock signal of constant basic frequency, their output waveforms are of rectangular shape synchronizing with the clock signal. The rectangular wave contains high harmonic components integral times the basic frequency. Thus, EMI noise will have peaks at primary, secondary and other high harmonic frequencies in addition to the basic wave.
Since clock signals used in the present electronic instruments are particularly generated by crystal oscillators, the stability in frequency is very high. Thus, EMI noise generated will also have increased peaks.
In this connection, to meet the EMI noise standards, it is required that the peak level in the EMI noise for each frequency band is reduced. Various measures have been made to reduce the peak in EMI noise. One of such measures is a method called xe2x80x9cSpread Spectrumxe2x80x9d. This method is to intentionally vary the frequency of clock signal to spread the distribution of frequency.
Usually, PLL is used to perform this spread spectrum method. However, PLL is not suitable for mounting on the semiconductor integrated circuits since it includes analog circuits such as VCO and the like.
It is therefore an object of the present invention to provide a clock generating circuit which can reduce EMI noise by generating a clock signal having its frequency that can be varied at a digital circuit, and a semiconductor integrated circuit using such a clock generating circuit.
In accordance with one aspect of the present invention, it provides a clock generating circuit comprising:
a delay circuit having output terminals, the delay circuit delaying an input clock signal and outputting delayed clock signals of different delay times respectively;
a selector selecting one of the output terminals; and
a control circuit controlling a selection operation in the selector,
wherein the control circuit supplies a group of bit output signals circulated in a predetermined cycle to the selector, and
wherein a cycle of an output clock signal sequentially outputted from each of the output terminals selected by the selector increases or decreases in accordance with the group of the bit output signals.
According to this aspect of the present invention, the clock signals of different delay times are sequentially output from the output terminals in the delay circuit, in accordance with the group of bit output signals circulated in a predetermined cycle. Thus, the cycle of output clock signals is increased or decreased to vary the frequencies in the output clock signals. The output clock signals are generated by the digital circuit and can yet be used to reduce the EMI noise.
The control circuit may include a counter circuit counting a given signal. In such a case, the control circuit may supply a bit output signal to the selector, the bit output signal selecting one of the output terminals that increases or decreases the delay time based on a count value from the counter circuit.
The selector may alternately select one of the output terminals providing minimum delay time and another of the output terminals based on the bit output signal. Thus, the cycle of output clock signals will alternately be increased and decreased.
The counter circuit may count one of the output clock signals having maximum delay time among the output clock signals outputted through the output terminals. Thus, the timing for switching the output terminals in the delay circuit will be synchronized with the output clock signals of maximum delay time. In such a manner, no hazard or spike will occur in the output clock signals.
The control circuit may include a linear feedback sift register having a bit output at least (N+1) where N is a number of bits in the bit output signal supplied to the selector. By supplying an output signal of N bits from the linear feedback sift register to the selector, that output signal of N bits may occur in the form of a pseudo-random number. Even though the output clock signal is divided for using as transfer clocks or the like, EMI noise can be reduced since the frequency in the divided clock signal varies at all times.
The clock generating circuit may comprise a logic gate into which a delayed clock signal from the one of the output terminals selected by the selector and the input clock signal are inputted to generate an output clock signal having an edge of which position is equal to a position of an edge of the input clock signal.
Although a hazard or spike occurs on switching between the output terminals in the delay circuit, the waveform causing the hazard or spike can be removed when the signal passes through the logic gate. In such a case, therefore, the counter circuit may count the input clock signal.
A buffer may be connected to each of front stage of the output terminals of the delay circuit and each buffer is connected to a load different from another. Thus, the difference between the delay times of the output clock signals from the output terminals will be shorter than the delay time difference obtained only by the buffer.
The delay circuit may comprise first and second delay circuits connected in series. In such a case, the first delay circuit may have first output terminals each of which outputs a first clock signal being delayed by a different delay time that is a multiple of a first delay time. The second delay circuit may have second output terminals further delaying the first clock signal outputted from any one of the first output terminals in the first delay circuit by a different delay time that is a multiple of a second delay time shorter than the first delay time, and outputting a second clock signal.
Thus, by selecting either of the first output terminals in the first delay circuit, a larger difference of delay time can be selected. On the other hand, by selecting either of the second output terminals in the second delay time, a smaller difference of delay time can be selected. As a result, an output clock signal having a sum delay time obtained by adding the larger and smaller delay times together can be generated.
M (Mxe2x89xa72) number of buffers may be connected in series to a front stage of each of the first output terminals in the first delay circuit, and at least one of buffer equal to or less then (Mxe2x88x921) number may be connected to a front stage of each of the second output terminals in the second delay circuit.
The clock generating circuit may further comprise a third delay circuit which is connected in series to the second delay circuit. The third delay circuit may have third output terminals, each of which further delays the second clock signal outputted from any one of the second output terminals in the second delay circuit by a different delay time that is a multiple of a third delay time shorter than the second delay time, and outputs a third clock signal.
By thus combining three types of delay times respectively selected at the first, second and third delay circuits, the number of types in delay time differences can be increased and also each of the delay time differences can more finely be set.
Each of a front stage of the third output terminals may be connected to a load different from another. Thus, the delay time differences can more finely be set since the minimum delay time difference in the second delay circuit depends on the delay time provided by the buffer while the minimum delay time difference in the second delay circuit depends on the time difference provided by the load.
The control circuit may comprise a timer circuit which sets a cycle of frequency in the output clock signal until the output clock signal gradually increases and decreases. When the set value in this timer circuit is varied, the cycle of frequency in the output clock signal until it gradually increases and decreases can be varied.
The control circuit may comprise:
an addition/subtraction circuit obtaining a bit output signal which gradually increases or decreases a frequency of the output clock signal; and
an addition/subtraction switching circuit switching between addition and subtraction in the addition/subtraction circuit.
When the addition/subtraction circuit is switched to the addition mode by the addition/subtraction switching circuit, the addition/subtraction circuit performs the addition to gradually increase the frequency of the output clock signal. On the contrary, when the addition/subtraction circuit is switched to the subtraction mode by the addition/subtraction switching circuit, the addition/subtraction circuit performs the subtraction to gradually decrease the frequency of the output clock signal.
The clock generating circuit may further comprise a phase comparison circuit which compares a phases difference between the input clock signal and the output clock signal. The phase comparison circuit may output a switching signal to the addition/subtraction circuit when the phase difference exceeds a specified value. Thus, the phase difference between the input and output clock signals is maintained within a constant range. This enables output clock signal of variable frequency to be generated without need of any huge memory capacity.
In accordance with another aspect of the present invention, it provides a semiconductor integrated circuit comprising the clock generating circuits having any one of the configurations as mentioned above. The clock generating circuit included in this semiconductor integrated circuit may generate a clock to be inputted to a logic circuit. However, it is preferable that a clock generated by the clock generating circuit is used as a transfer clock signal in an output circuit which outputs a signal from the logic circuit to outside. Since the frequency of a signal outputted from the output circuit and then transmitted through the wiring of a printed circuit board is variable, EMI noise emitted from the wiring of the printed circuit board can be reduced.